This application claims priority under 35 U.S.C. xc2xa7119 from Korean Patent Application No. 2001-41939, filed on Jul. 12, 2001, the entirety of which is hereby incorporated by reference as if fully set forth herein.
1. Field of the Invention
The present invention relates to a method for forming a fuse, and more particularly to method for forming a fuse that is cut when a bad cell is repaired during the manufacture of a semiconductor device.
2. Description of the Related Art
Due to the widespread usage of information devices, such as computers, developments in semiconductor memory devices are rapidly progressing so as to provide a semiconductor device having a high memory storage capacity and a faster operating speed. To this end, technology in the art is focused on developing and realizing memory devices having a degree of integration, response speed, and reliability.
A semiconductor device generally may be manufactured by using a wafer composed of silicon. In general, the manufacturing technology of semiconductor devices includes a fabrication process and an assembly process. In the fabrication process, a plurality of cells having integrated circuits are manufactured by repeatedly forming predetermined patterns on a wafer. In the assembly process, the wafer having the cells thereon is cut into chip units, and then the chips are packaged. An electrical die sorting (hereinafter, referred to as xe2x80x9cEDSxe2x80x9d) process is performed between the fabrication process and the assembly process to inspect the electrical properties of the cell formed on the wafer.
In the EDS process, each cell in a chip is inspected to determine whether the cell has good or bad electrical properties. Particularly, a cell turning out to have bad electrical properties is removed before the assembly process is carried out. By detecting the bad cell(s) prior to use and repairing the bad cell(s) effort and a cost may be reduced in the manufacturing of semiconductor devices.
The EDS process includes a pre-laser test, a repairing process and a post-laser test. In the pre-laser test, the bad cell is selected and data related to the bad cell are generated. The repairing process repairs the bad cell. That is, the repairing process uses a laser beam to cut a fuse connecting the bad cell, and the bad cell is replaced with a redundancy cell. The post-laser test re-inspects a repaired cell.
For example, a static random access memory (SRAM) device uses a gate polysilicon layer as the fuse. However, it is not easy to use the gate polysilicon layer as the fuse because an insulating interlayer has a step difference of about 20,000 xc3x85 or more when the SRAM device is comprised of a multi-layer structure. Accordingly, when the SRAM device is comprised of the multi-layer structure, the fuse is formed in a via hole, or a portion of barrier metal layer formed on a top surface of a substrate is used as the fuse.
An example of a method for forming a fuse in the via hole is disclosed in U.S. Pat. No. 6,175,145 (issued to Lee et al.).
FIGS. 1 and 2 are sectional views illustrating a conventional method for forming the fuse by using a portion of barrier metal layer.
FIG. 1 shows a fence A which is formed on a circumference of fuse 10. The fence A is formed on a region where the fuse 10 is formed because by-products generated when an insulating layer 12 is etched are adhered to an insulating layer residue. Therefore, the fence A decreases a process margin when the fuse 10 is cut due to the step difference of the fence A.
FIG. 2 shows a state that the fence is removed from the fuse 10. For that reason, the process margin is secured by means of removing the fence A.
As described above, a removing process of the fence A is performed in order to form the fuse 10. However, the removing process of the fence A lowers the process efficiency. Particularly, when the semiconductor device has a multi-layer structure, the conventional method results in a lowering of process efficiency.
The present invention has been made to address the above problems of the prior art. Therefore, it is an object of the present invention to provide a simplified method for forming a fuse.
In one aspect, there is provided a method for forming a fuse. A barrier metal layer and a metal layer are sequentially formed on a substrate and the metal layer and the barrier metal layer in a first region are sequentially etched to form a metal wiring pattern and to partially expose the substrate. Then, an insulating layer is continuously formed on the metal wiring pattern and the partially exposed substrate. The insulating layer in a second region is etched by using an etching gas including a fluorocarbon-type compound and a fluorosilicate-type compound. The etching gas substantially suppresses a generation of by-products. Thus, a fuse pattern region is defined by exposing the metal wiring pattern in the second predetermined region. A residue of the insulating layer remains at a lower portion of a side wall of the metal wiring pattern. The metal layer in the metal wiring pattern of the fuse pattern is etched to form the fuse by exposing a top surface of the barrier metal layer under the metal layer.
There is also provided another method for forming a fuse, wherein a barrier metal layer and a metal layer are sequentially formed on a substrate having a lower structure formed thereon. The metal layer and the barrier metal layer in a first region are sequentially etched to form a metal wiring pattern and to partially expose the lower structure. An insulating layer is continuously formed on the metal layer and the partially exposed lower structure. The insulating layer in a second region and the lower structure under the insulating layer is sequentially etched by using an etching gas including a fluorocarbon-type compound and a fluorosilicate-type compound. The etching gas substantially suppresses a generation of by-products. Thus, a fuse pattern region is defined by exposing the metal wiring pattern in the second region. A residue of the insulating layer remains at a lower portion of a side wall of the metal wiring pattern. The metal layer in the metal wiring pattern of the fuse pattern is etched to form the fuse by exposing a top surface of the barrier metal layer under the metal layer.
There is provided still another method for forming a fuse wherein a barrier metal layer and a metal layer are sequentially formed on a substrate having a lower structure formed thereon. The metal layer and the barrier metal layer in a first region are sequentially etched to form a metal wiring pattern and to partially expose the lower structure. An insulating layer is formed continuously on the metal layer and the partially exposed lower structure. After forming a photoresist pattern on the insulating layer to expose the insulating layer in a second predetermined region of the insulating layer, the insulating layer in the second predetermined region and the lower structure under the insulating layer are sequentially etched by using an etching gas including a fluorocarbon-type compound and a fluorosilicate-type compound. The etching gas substantially suppresses a generation of by-products. Thus, a fuse pattern region is defined by exposing the metal wiring pattern in the second region. A residue of the insulating layer remains at a lower portion of a side wall of the metal wiring pattern. A portion of the metal layer of the metal wiring pattern is dry etched with a second etching gas. After completely removing the photoresist pattern, a remaining metal layer is wet etched. The wet etching has an etching selectivity of the metal layer with respect to the barrier metal layer. The fuse is formed by exposing a top surface of the barrier metal layer under the metal layer.
As disclosed herein, when the insulating layer is etched so as to form a fuse pattern, the generation of the by-products such as polymer is suppressed. Since the fence is not formed, the removing process of the fence is not necessary. Particularly, the methods disclosed herein are applicable to the manufacturing of a semiconductor device having a multi-layer structure.